View M470T2953BS0-CD5CC_286659.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

256MB, 512MB, 1GB Unbuffered SODIMMs
DDR2 SDRAM
DDR2 Unbuffered SODIMM
200pin Unbuffered SODIMM based on 512Mb B-die 64bit Non-ECC
INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS, AND IS SUBJECT TO CHANGE WITHOUT NOTICE. NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL INFORMATION IN THIS DOCUMENT IS PROVIDED ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND.
1. For updates or additional information about Samsung products, contact your nearest Samsung office. 2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar applications where Product failure couldresult in loss of life or personal or physical harm, or any military or defense application, or any governmental procurement to which special terms or provisions may apply.
* Samsung Electronics reserves the right to change products or specification without notice.
Rev. 1.5 Aug. 2005
256MB, 512MB, 1GB Unbuffered SODIMMs
DDR2 Unbuffered SODIMM Ordering Information
Part Number M470T3354BG(Z)3-CD5/CC M470T3354BG(Z)0-CD5/CC M470T3354BZ3-LD5/CC M470T3354BZ0-LD5/CC M470T6554BG(Z)3-CD5/CC M470T6554BG(Z)0-CD5/CC M470T6554BZ3-LD5/CC M470T6554BZ0-LD5/CC M470T2953BS(Y)3-CD5/CC M470T2953BS(Y)0-CD5/CC M470T2953BY3-LD5/CC M470T2953BY0-LD5/CC Density 256MB 256MB 256MB 256MB 512MB 512MB 512MB 512MB 1GB 1GB 1GB 1GB Organization 32Mx64 32Mx64 32Mx64 32Mx64 64Mx64 64Mx64 64Mx64 64Mx64 128Mx64 128Mx64 128Mx64 128Mx64 Component Composition 32Mx16(K4T51163QB)*4 32Mx16(K4T51163QB)*4 32Mx16(K4T51163QB)*4 32Mx16(K4T51163QB)*4 32Mx16(K4T51163QB)*8 32Mx16(K4T51163QB)*8 32Mx16(K4T51163QB)*8 32Mx16(K4T51163QB)*8 64Mx8(K4T51083QB)*16 64Mx8(K4T51083QB)*16 64Mx8(K4T51083QB)*16 64Mx8(K4T51083QB)*16
DDR2 SDRAM
Number of Rank 1 1 1 1 2 2 2 2 2 2 2 2 Height 30mm 30mm 30mm 30mm 30mm 30mm 30mm 30mm 30mm 30mm 30mm 30mm
Note: "Z" and "Y" of Part number(11th digit) stand for Lead-free products. Note: "3" of Part number(12th digit) stand for Dummy Pad PCB products.
Features
* Performance range
D5(DDR2-533) Speed@CL3 Speed@CL4 CL-tRCD-tRP 400 533 4-4-4 CC(DDR2-400) 400 400 3-3-3 Unit Mbps Mbps CK
* JEDEC standard 1.8V 0.1V Power Supply * VDDQ = 1.8V 0.1V * 200 MHz fCK for 400Mb/sec/pin, 267MHz fCK for 533Mb/sec/pin * 4 Banks * Posted CAS * Programmable CAS Latency: 3, 4, 5 * Programmable Additive Latency: 0, 1 , 2 , 3 and 4 * Write Latency(WL) = Read Latency(RL) -1 * Burst Length: 4 , 8(Interleave/nibble sequential) * Programmable Sequential / Interleave Burst Mode * Bi-directional Differential Data-Strobe (Single-ended data-strobe is an optional feature) * Off-Chip Driver(OCD) Impedance Adjustment * On Die Termination * Average Refresh Period 7.8us at lower than a TCASE 85C, 3.9us at 85C < TCASE < 95 C - support High Temperature Self-Refresh rate enable feature * Package: 60ball FBGA - 64Mx8 , 84ball FBGA - 32Mx16 * All of Lead-free products are compliant for RoHS
Note: For detailed DDR2 SDRAM operation, please refer to Samsung's Device operation & Timing diagram.
Address Configuration
Organization 64Mx8(512Mb) based Module 32Mx16(512Mb) based Module Row Address A0-A13 A0-A12 Column Address A0-A9 A0-A9 Bank Address BA0-BA1 BA0-BA1 Auto Precharge A10 A10
Rev. 1.5 Aug. 2005
256MB, 512MB, 1GB Unbuffered SODIMMs
Pin Configurations (Front side/Back side)
Pin
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49
DDR2 SDRAM
Pin
102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150
Front
VREF VSS DQ0 DQ1 VSS DQS0 DQS0 VSS DQ2 DQ3 VSS DQ8 DQ9 VSS DQS1 DQS1 VSS DQ10 DQ11 VSS VSS DQ16 DQ17 VSS DQS2
Pin
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50
Back
VSS DQ4 DQ5 VSS DM0 VSS DQ6 DQ7 VSS DQ12 DQ13 VSS DM1 VSS CK0 CK0 VSS DQ14 DQ15 VSS VSS DQ20 DQ21 VSS NC
Pin
51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99
Front
DQS2 VSS DQ18 DQ19 VSS DQ24 DQ25 VSS DM3 NC VSS DQ26 DQ27 VSS CKE0 VDD NC BA2 VDD A12 A9 A8 VDD A5 A3
Pin
52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100
Back
DM2 VSS DQ22 DQ23 VSS DQ28 DQ29 VSS DQS3 DQS3 VSS DQ30 DQ31 VSS NC/CKE1 VDD NC NC VDD A11 A7 A6 VDD A4 A2
Pin
101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149
Front
A1 VDD A10/AP BA0 WE VDD CAS NC/S1 VDD NC/ODT1 VSS DQ32 DQ33 VSS DQS4 DQS4 VSS DQ34 DQ35 VSS DQ40 DQ41 VSS DM5 VSS
Back
A0 VDD BA1 RAS S0 VDD ODT0 A13 VDD NC VSS DQ36 DQ37 VSS DM4 VSS DQ38 DQ39 VSS DQ44 DQ45 VSS DQS5 DQS5 VSS
Pin
151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199
Front
DQ42 DQ43 VSS DQ48 DQ49 VSS NC, TEST VSS DQS6 DQS6 VSS DQ50 DQ51 VSS DQ56 DQ57 VSS DM7 VSS DQ58 DQ59 VSS SDA SCL VDDSPD
Pin
152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200
Back
DQ46 DQ47 VSS DQ52 DQ53 VSS CK1 CK1 VSS DM6 VSS DQ54 DQ55 VSS DQ60 DQ61 VSS DQS7 DQS7 VSS DQ62 DQ63 VSS SA0 SA1
Note : NC = No Connect; NC, TEST(pin 163)is for bus analysis tool and is not connected on normal memory modules.
Pin Description
Pin Name
CK0,CK1 CK0,CK1 CKE0,CKE1 RAS CAS WE S0,S1 A0~A9, A11~A13 A10/AP BA0,BA1 ODT0,ODT1 SCL
Function
Clock Inputs, positive line Clock Inputs, negative line Clock Enables Row Address Strobe Column Address Strobe Write Enable Chip Selects Address Inputs Address Input/Autoprecharge SDRAM Bank Address On-die termination control Serial Presence Detect(SPD) Clock Input
Pin Name
SDA SA1,SA0 DQ0~DQ63 DM0~DM7 DQS0~DQS7 DQS0~DQS7 TEST VDD VSS VREF VDDSPD NC SPD Data Input/Output SPD address Data Input/Output Data Masks Data strobes
Function
Data strobes complement Logic Analyzer specific test pin (No connect on So-DIMM) Core and I/O Power Ground Input/Output Reference SPD Power Spare pins, No connect
Rev. 1.5 Aug. 2005
256MB, 512MB, 1GB Unbuffered SODIMMs
Input/Output Functional Description
Symbol CK0-CK1 CK0-CK1 CKE0-CKE1 Type Input Function
DDR2 SDRAM
The system clock inputs. All address and command lines are sampled on the cross point of the rising edge of CK and falling edge of CK . A Delay Locked Loop (DLL) circuit is driven from the clock input and output timing for read operations is synchronized to the input clock. Activates the DDR2 SDRAM CK signal when high and deactivates the CK signal when low, By deactivating the clocks, CKE low initiates the Power Down mode or the Self Refesh mode. Enables the associated DDR2 SDRAM command decoder when low and disables the command decoder when high. When the command decoder is disabled, new commands are ignored but previous operations continue. Rank 0 is selected by S0, Rank 1 is selected by S1. Ranks are also called "Physical banks". When sampled at the cross point of the rising edge of CK and falling edge of CK, CAS, RAS, and WE define the operation to be executed by the SDRAM. Selects which DDR2 SDRAM internal bank is activated. Asserts on-die termination for DQ, DM, DQS, and DQS signals if enabled via the DDR2 SDRAM Extended Mode Register Set (EMRS). During a Bank Activate command cycle, defines the row address when sampled at the cross point of the rising edge of CK and falling edge of CK. During a Read or Write command cycle, defines the column address when sampled at the cross point of the rising edge of CK and falling edge of CK. In addition to the column address, AP is used to invoke autoprecharge operation at the end of the burst read or write cycle. If AP is high, autoprecharge is selected and BA0-BAn defines the bank to be precharged. If AP is low, autoprecharge is disabled. During a Precharge command cycle, AP is used in conjunction with BA0-BAn to control which bank(s) to precharge. If AP is high, all banks will be pecharged regardiess of the state of BA0-BAn inputs. If AP is low, then BA0-BAn are used to define which bank to precharge. Data Input/Output pins. The data write masks, associated with one data byte. In Write mode, DM operates as a byte mask by allowing input data to be written if it is low but blocks the write operation if it is high. In Read mode, DM lines have no effect. The data strobes, associated with one data byte, sourced with data transfers. In Write mode, the data strobe is sourced by the controller and is centered in the data window. In Read mode, the data strobe is sourced by the DDR2 SDRAMs and is sent at the leading edge of the data window. DQS signals are complements, and timing is relative to the crosspoint of respective DQS and DQS If the module is to be operated in single ended strobe mode, all DQS signals must be tied on the system board to VSS and DDR2 SDRAM mode registers programmed appropriately. Power supplies for core, I/O, Serial Presence Detect, and ground for the module. This is a bidirectional pin used to transfer data into or out of the SPD EEPROM. A resistor must be connected to VDD to act as a pull up. This signal is used to clock data into and out of the SPD EEPROM. A resistor may be connected from SCL to VDD to act as a pull up. Address pins used to select the Serial Presence Detect base address. The TEST pin is reserved for bus analysis tools and is not connected on normal memory modules(SO-DIMMs).
Input
S0-S1
Input
RAS, CAS, WE BA0~BA1 ODT0~ODT1
Input Input Input
A0~A9, A10/AP, A11~A13
Input
DQ0~DQ63 DM0~DM7
In/Out Input
DQS0~DQS7 DQS0~DQS7
In/Out
VDD,VDD SPD,VSS SDA SCL SA0~SA1 TEST
Supply In/Out Input Input In/Out
Rev. 1.5 Aug. 2005
256MB, 512MB, 1GB Unbuffered SODIMMs
M470T6554BG(Z)3/M470T6554BG(Z)0
3 + 5% ODT1 ODT0 CKE1 CKE0 S1 S0 DQS0 DQS0 DM0 LDQS CS C K LDQS E LDM I/O 0 I/O 1 D0 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 UDQS UDQS UDM I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15 LDQS CS C K LDQS E LDM I/O 0 I/O 1 D1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 UDQS UDQS UDM I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15
O D T
DDR2 SDRAM
Functional Block Diagram: 512MB, 64Mx64 Module(Populated as 2 rank of x16 DDR2 SDRAMs)
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7
DQS1 DQS1 DM1
DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15
LDQS CS C K LDQS E LDM I/O 0 I/O 1 D4 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 UDQS UDQS UDM I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15 LDQS CS C K LDQS E LDM I/O 0 I/O 1 D5 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 UDQS UDQS UDM I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15
O D T
DQS4 DQS4 DM4
DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39
DQS5 DQS5 DM5
DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47
LDQS CS C K LDQS E LDM I/O 0 I/O 1 D2 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 UDQS UDQS UDM I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15 LDQS CS C K LDQS E LDM I/O 0 I/O 1 D3 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 UDQS UDQS UDM I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15
O D T
LDQS CS C K LDQS E LDM I/O 0 I/O 1 D6 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 UDQS UDQS UDM I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15 LDQS CS C K LDQS E LDM I/O 0 I/O 1 D7 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 UDQS UDQS UDM I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15
O D T
DQS2 DQS2 DM2
O D T
O D T
DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23
DQS6 DQS6 DM6
O D T
O D T
DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55
DQS3 DQS3 DM3
DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31
DQS7 DQS7 DM7
DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63
3 + 5% BA0 - BA1 A0 - A13 RAS CAS WE DDR2 SDRAMs D0 - D7 DDR2 SDRAMs D0 - D7 DDR2 SDRAMs D0 - D7 DDR2 SDRAMs D0 - D7 DDR2 SDRAMs D0 - D7 SCL SA0 SA1 SCL A0 SPD A1 A2 WP
SDA
* Clock Wiring
VDDSPD VREF VDD VSS Serial PD DDR2 SDRAMs D0 - D7 DDR2 SDRAMs D0 - D7, VDD and VDDQ DDR2 SDRAMs D0 - D7, SPD
Clock Input *CK0/CK0 *CK1/CK1
DDR2 SDRAMs 4 DDR2 SDRAMs 4 DDR2 SDRAMs
* Wire per Clock Loading Table/Wiring Diagrams
Notes : 1. DQ,DM, DQS/DQS resistors : 22 Ohms 5%. 2. BAx, Ax, RAS, CAS, WE resistors : 3.0 Ohms 5%.
Rev. 1.5 Aug. 2005
256MB, 512MB, 1GB Unbuffered SODIMMs
M470T3354BG(Z)3/M470T3354BG(Z)0
3 + 5% CKE0 ODT0 S0 DQS0 DQS0 DM0 LDQS CS O D LDQS T LDM I/O 0 I/O 1 D0 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 UDQS UDQS UDM I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15 LDQS CS O D LDQS T LDM I/O 0 I/O 1 D1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 UDQS UDQS UDM I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15
C K E
DDR2 SDRAM
Functional Block Diagram: 256MB, 32Mx64 Module(Populated as 1 rank of x16 DDR2 SDRAMs)
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7
DQS4 DQS4 DM4
DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39
DQS1 DQS1 DM1
DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15
DQS5 DQS5 DM5
DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47
LDQS CS O D LDQS T LDM I/O 0 I/O 1 D2 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 UDQS UDQS UDM I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15 LDQS CS O D LDQS T LDM I/O 0 I/O 1 D3 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 UDQS UDQS UDM I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15
C K E
DQS2 DQS2 DM2
C K E
DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23
DQS6 DQS6 DM6
C K E
DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55
DQS3 DQS3 DM3
DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31
DQS7 DQS7 DM7
DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63
3 BA0 - BA1 A0 - A13 RAS CAS WE DDR2 SDRAMs D0 - D3 DDR2 SDRAMs D0 - D3 DDR2 SDRAMs D0 - D3 DDR2 SDRAMs D0 - D3 DDR2 SDRAMs D0 - D3
SCL SA0 SA1
SCL A0 SPD A1 A2 WP
SDA
* Clock Wiring
VDDSPD VREF VDD VSS Serial PD DDR2 SDRAMs D0 - D3 DDR2 SDRAMs D0 - D3, VDD and VDDQ DDR2 SDRAMs D0 - D3, SPD
Clock Input *CK0/CK0 *CK1/CK1
DDR2 SDRAMs 2 DDR2 SDRAMs 2 DDR2 SDRAMs
* Wire per Clock Loading Table/Wiring Diagrams
Notes : 1. DQ,DM, DQS/DQS resistors : 22 Ohms 5%. 2. BAx, Ax, RAS, CAS, WE resistors : 3.0 Ohms 5%.
Rev. 1.5 Aug. 2005
256MB, 512MB, 1GB Unbuffered SODIMMs
M470T2953BS(Y)3/M470T2953BS(Y)0
3 + 5% CKE1 ODT1 S1 CKE0 ODT0 S0 DQS0 DQS0 DM0 DQS DQS DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
CS0 O D T 0 C K E 0
DDR2 SDRAM
Functional Block Diagram: 1GB, 128Mx64 Module(Populated as 2 ranks of x8 DDR2 SDRAMs)
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7
D0
DQS DQS DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
CS1 O D T 1
C K E 1
DQS4 DQS4 DM4
D8
DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39
DQS DQS DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
CS0 O D T 0
C K E 0
D4
DQS DQS DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
CS1 O D T 1
C K E 1
D12
DQS1 DQS1 DM1
DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15
CS0 O DQS DQS D DM T 0 I/O 8 I/O 9 D1 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15
C K E 0
CS1 O DQS DQS D DM T 1 I/O 8 I/O 9 D9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15
C K E 1
DQS5 DQS5 DM5
DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47
DQS DQS DM I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15
CS0 O D T 0
C K E 0
D5
DQS DQS DM I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15
CS1 O D T 1
C K E 1
D13
DQS2 DQS2 DM2
DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23
DQS DQS DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
CS0 O D T 0
C K E 0
D2
DQS DQS DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
CS1 O D T 1
C K E 1
DQS6 DQS6 DM6
D10
DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55
DQS DQS DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
CS0 O D T 0
C K E 0
D6
DQS DQS DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
CS1 O D T 1
C K E 1
D14
DQS3 DQS3 DM3
DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31
CS0 O DQS D DQS T DM 0 I/O 8 I/O 9 D3 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15
C K E 0
CS1 O DQS D DQS T DM 1 I/O 8 I/O 9 D11 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15
C K E 1
DQS7 DQS7 DM7
DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63
DQS DQS DM I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15
CS0 O D T 0
C K E 0
D7
DQS DQS DM I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15
CS1 O D T 1
C K E 1
D15
10 + 5% BA0 - BA1 A0 - A13 RAS CAS WE DDR2 SDRAMs D0 - D15 DDR2 SDRAMs D0 - D15 DDR2 SDRAMs D0 - D15 DDR2 SDRAMs D0 - D15 DDR2 SDRAMs D0 - D15 SCL SA0 SA1 SCL A0 SPD A1 A2 WP
* Clock Wiring Clock Input
SDA
DDR2 SDRAMs 8 DDR2 SDRAMs 8 DDR2 SDRAMs
*CK0/CK0 *CK1/CK1
* Wire per Clock Loading Table/Wiring Diagrams
VDDSPD VREF VDD VSS
Serial PD DDR2 SDRAMs D0 - D15 DDR2 SDRAMs D0 - D15, VDD and VDDQ DDR2 SDRAMs D0 - D15, SPD
Notes : 1. DQ,DM, DQS/DQS resistors : 22 Ohms 5%. 2. BAx, Ax, RAS, CAS, WE resistors : 10 Ohms 5%.
Rev. 1.5 Aug. 2005
256MB, 512MB, 1GB Unbuffered SODIMMs
Absolute Maximum DC Ratings
Symbol VDD VDDQ VDDL VIN, VOUT TSTG Parameter Voltage on VDD pin relative to VSS Voltage on VDDQ pin relative to VSS Voltage on VDDL pin relative to VSS Voltage on any pin relative to VSS Storage Temperature Rating - 1.0 V ~ 2.3 V - 0.5 V ~ 2.3 V - 0.5 V ~ 2.3 V - 0.5 V ~ 2.3 V -55 to +100
DDR2 SDRAM
Units V V V V C Notes 1 1 1 1 1, 2
Note : 1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. Storage Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JESD51-2 standard.
AC & DC Operating Conditions
Recommended DC Operating Conditions (SSTL - 1.8)
Symbol VDD VDDL VDDQ VREF VTT Supply Voltage Supply Voltage for DLL Supply Voltage for Output Input Reference Voltage Termination Voltage Parameter Rating Min. 1.7 1.7 1.7 0.49*VDDQ VREF-0.04 Typ. 1.8 1.8 1.8 0.50*VDDQ VREF Max. 1.9 1.9 1.9 0.51*VDDQ VREF+0.04 Units V V V mV V 4 4 1,2 3 Notes
Note : There is no specific device VDD supply voltage requirement for SSTL-1.8 compliance. However under all conditions VDDQ must be less than or equal to VDD. 1. The value of VREF may be selected by the user to provide optimum noise margin in the system. Typically the value of VREF is expected to be about 0.5 x VDDQ of the transmitting device and VREF is expected to track variations in VDDQ. 2. Peak to peak AC noise on VREF may not exceed +/-2% VREF(DC). 3. VTT of transmitting device must track VREF of receiving device. 4. AC parameters are measured with VDD, VDDQ and VDDL tied together.
Rev. 1.5 Aug. 2005
256MB, 512MB, 1GB Unbuffered SODIMMs
Operating Temperature Condition
Symbol TOPER Parameter Operating Temperature Rating 0 to 95 Units C
DDR2 SDRAM
Notes 1, 2, 3
Note : 1. Operating Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JESD51.2 standard. 2. At 0 - 85 C, operation temperature range are the temperature which all DRAM specification will be supported. 3. At 85 - 95 C operation temperature range, doubling refresh commands in frequency to a 32ms period ( tREFI=3.9 us ) is required, and to enter to self refresh mode at this temperature range, an EMRS command is required to change internal refresh rate.
Input DC Logic Level
Symbol VIH(DC) VIL(DC) Parameter DC input logic high DC input logic low Min. VREF + 0.125 - 0.3 Max. VDDQ + 0.3 VREF - 0.125 Units V V Notes
Input AC Logic Level
Symbol VIH(AC) VIL(AC) Parameter AC input logic high AC input logic low Min. VREF + 0.250 Max. VREF - 0.250 Units V V Notes
AC Input Test Conditions
Symbol VREF VSWING(MAX) SLEW Input reference voltage Input signal maximum peak to peak swing Input signal minimum slew rate Condition Value 0.5 * VDDQ 1.0 1.0 Units V V V/ns Notes 1 1 2, 3
Notes: 1. Input waveform timing is referenced to the input signal crossing through the VIH/IL(AC) level applied to the device under test. 2. The input signal minimum slew rate is to be maintained over the range from VREF to VIH(AC) min for rising edges and the range from VREF to VIL(AC) max for falling edges as shown in the below figure. 3. AC timings are referenced with input waveforms switching from VIL(AC) to VIH(AC) on the positive transitions and VIH(AC) to VIL(AC) on the negative transitions.
VDDQ VIH(AC) min VSWING(MAX) VIH(DC) min VREF VIL(DC) max VIL(AC) max delta TF Falling Slew = VREF - VIL(AC) max delta TF delta TR Rising Slew = VSS VIH(AC) min - VREF delta TR
< AC Input Test Signal Waveform >
Rev. 1.5 Aug. 2005
256MB, 512MB, 1GB Unbuffered SODIMMs
IDD Specification Parameters Definition
(IDD values are for full operating range of Voltage and Temperature)
Symbol IDD0 Proposed Conditions
DDR2 SDRAM
Units mA
Notes
Operating one bank active-precharge current; tCK = tCK(IDD), tRC = tRC(IDD), tRAS = tRASmin(IDD); CKE is HIGH, CS\ is HIGH between valid commands; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING Operating one bank active-read-precharge current; IOUT = 0mA; BL = 4, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRC = tRC (IDD), tRAS = tRASmin(IDD), tRCD = tRCD(IDD); CKE is HIGH, CS\ is HIGH between valid commands; Address bus inputs are SWITCHING; Data pattern is same as IDD4W Precharge power-down current; All banks idle; tCK = tCK(IDD); CKE is LOW; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING Precharge quiet standby current; All banks idle; tCK = tCK(IDD); CKE is HIGH, CS\ is HIGH; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING Precharge standby current; All banks idle; tCK = tCK(IDD); CKE is HIGH, CS\ is HIGH; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING Active power-down current; All banks open; tCK = tCK(IDD); CKE is LOW; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING Fast PDN Exit MRS(12) = 0mA Slow PDN Exit MRS(12) = 1mA
IDD1
mA
IDD2P
mA
IDD2Q
mA
IDD2N
mA mA mA mA
IDD3P
IDD3N
Active standby current; All banks open; tCK = tCK(IDD), tRAS = tRASmax(IDD), tRP = tRP(IDD); CKE is HIGH, CS\ is HIGH between valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING Operating burst write current; All banks open, Continuous burst writes; BL = 4, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRAS = tRASmax(IDD), tRP = tRP(IDD); CKE is HIGH, CS\ is HIGH between valid commands; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING Operating burst read current; All banks open, Continuous burst reads, IOUT = 0mA; BL = 4, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRAS = tRASmax(IDD), tRP = tRP(IDD); CKE is HIGH, CS\ is HIGH between valid commands; Address bus inputs are SWITCHING; Data pattern is same as IDD4W Burst auto refresh current; tCK = tCK(IDD); Refresh command at every tRFC(IDD) interval; CKE is HIGH, CS\ is HIGH between valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING Self refresh current; CK and CK\ at 0V; CKE 0.2V; Other control and address bus inputs are FLOATING; Data bus inputs are FLOATING Normal Low Power
IDD4W
mA
IDD4R
mA
IDD5B
mA mA mA
IDD6
IDD7
Operating bank interleave read current; All bank interleaving reads, IOUT = 0mA; BL = 4, CL = CL(IDD), AL = tRCD(IDD)-1*tCK(IDD); tCK = tCK(IDD), tRC = tRC(IDD), tRRD = tRRD(IDD), tFAW = tFAW(IDD), tRCD = 1*tCK(IDD); CKE is HIGH, CS\ is HIGH between valid commands; Address bus inputs are STABLE during DESELECTs; Data pattern is same as IDD4R; Refer to the following page for detailed timing conditions
mA
Rev. 1.5 Aug. 2005
256MB, 512MB, 1GB Unbuffered SODIMMs
Operating Current Table(1-1) (TA=0oC, VDD= 1.9V)
M470T6554BG(Z)3/M470T6554BG(Z)0 : 64Mx64 512MB Module
Symbol IDD0 IDD1 IDD2P IDD2Q IDD2N IDD3P-F IDD3P-S IDD3N IDD4W IDD4R IDD5B IDD6 IDD7 CD5 (DDR533@CL=4) 760 860 64 200 240 240 120 560 1,200 1,100 1,060 44 1,840 LD5 (DDR533@CL=4) 460 560 64 200 200 120 120 260 700 700 860 40 1,060 CCC (DDR400@CL=3) 720 760 64 200 240 240 120 520 1,000 940 1,000 44 1,760
DDR2 SDRAM
LCC (DDR400@CL=3) 460 520 64 200 200 120 120 260 700 700 860 40 1,060
Unit mA mA mA mA mA mA mA mA mA mA mA mA mA
Notes
* Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.
M470T3354BG(Z)3/M470T3354BG(Z)0 : 32Mx64 256MB Module
Symbol IDD0 IDD1 IDD2P IDD2Q IDD2N IDD3P-F IDD3P-S IDD3N IDD4W IDD4R IDD5B IDD6 IDD7 CD5 (DDR533@CL=4) 480 580 32 100 120 120 60 280 920 820 780 22 1,560 LD5 (DDR533@CL=4) 360 460 32 100 100 60 60 160 600 600 760 20 960 CCC (DDR400@CL=3) 460 500 32 100 120 120 60 260 740 680 740 22 1,500 LCC (DDR400@CL=3) 360 420 32 100 100 60 60 160 520 520 760 20 960 Unit mA mA mA mA mA mA mA mA mA mA mA mA mA Notes
* Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.
Rev. 1.5 Aug. 2005
256MB, 512MB, 1GB Unbuffered SODIMMs
Operating Current Table(1-2) (TA=0oC, VDD= 1.9V)
M470T2953BS(Y)3/M470T2953BS(Y)0 : 128Mx64 1GB Module
Symbol IDD0 IDD1 IDD2P IDD2Q IDD2N IDD3P-F IDD3P-S IDD3N IDD4W IDD4R IDD5B IDD6 IDD7 CD5 (DDR533@CL=4) 1,360 1,440 128 400 480 480 240 1,120 2,160 2,000 2,120 88 2,760 LD5 (DDR533@CL=4) 760 920 128 400 400 240 240 520 1,160 1,160 1,720 80 1,960 CCC (DDR400@CL=3) 1,280 1,320 128 400 480 480 240 1,040 1,680 1,680 2,000 88 2,680
DDR2 SDRAM
LCC (DDR400@CL=3) 760 840 128 400 400 240 240 520 1,000 1,000 1,720 80 1,960
Unit mA mA mA mA mA mA mA mA mA mA mA mA mA
Notes
* Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.
Input/Output Capacitance(VDD=1.8V, VDDQ=1.8V, TA=25oC)
Parameter Non-ECC Input capacitance, CK and CK Input capacitance, CKE , CS, Addr, RAS, CAS, WE Input/output capacitance, DQ, DM, DQS, DQS Symbol CCK CI CIO Min Max Min Max Min Max Units M470T6554BG(Z)3 M470T6554BG(Z)0 32 34 10 M470T3354BG(Z)3 M470T3354BG(Z)0 24 34 6 M470T2953BS(Y)3 M470T2953BS(Y)0 48 42 10 pF
* DM is internally loaded to match DQ and DQS identically.
Rev. 1.5 Aug. 2005
256MB, 512MB, 1GB Unbuffered SODIMMs
Electrical Characteristics & AC Timing for DDR2-533/400 SDRAM
(0 C < TCASE < 95 C; VDDQ = 1.8V + 0.1V; VDD = 1.8V + 0.1V)
DDR2 SDRAM
Refresh Parameters by Device Density
Parameter Refresh to active/Refresh command time Average periodic refresh interval tRFC tREFI 0 C TCASE 85C 85 C < TCASE 95C Symbol 256Mb 75 7.8 3.9 512Mb 105 7.8 3.9 1Gb 127.5 7.8 3.9 2Gb 195 7.8 3.9 4Gb tbd 7.8 3.9 Units ns s s
Speed Bins and CL, tRCD, tRP, tRC and tRAS for Corresponding Bin
Speed Bin (CL - tRCD - tRP) Parameter tCK, CL=3 tCK, CL=4 tCK, CL=5 tRCD tRP tRC tRAS min 5 3.75 15 15 55 40
70000
DDR2-533(D5) 4-4-4 max 8 8 min 5 5 15 15 55 40
DDR2-400(CC) 3-3-3 max 8 8 ns ns ns ns ns ns
70000
Units
ns
Rev. 1.5 Aug. 2005
256MB, 512MB, 1GB Unbuffered SODIMMs
Timing Parameters by Speed Grade
(Refer to notes for informations related to this table at the bottom) Parameter DQ output access time from CK/CK DQS output access time from CK/CK CK high-level width CK low-level width CK half period Clock cycle time, CL=x DQ and DM input hold time DQ and DM input setup time Control & Address input pulse width for each input DQ and DM input pulse width for each input Data-out high-impedance time from CK/CK DQS low-impedance time from CK/CK DQ low-impedance time from CK/CK DQS-DQ skew for DQS and associated DQ signals DQ hold skew factor DQ/DQS output hold time from DQS Write command to first DQS latching transition DQS input high pulse width DQS input low pulse width DQS falling edge to CK setup time DQS falling edge hold time from CK Mode register set command cycle time Write postamble Write preamble Address and control input hold time Address and control input setup time Read preamble Read postamble Symbol tAC tDQSCK tCH tCL tHP tCK tDH tDS tIPW tDIPW tHZ tLZ(DQS) tLZ(DQ) tDQSQ tQHS tQH tDQSS tDQSH tDQSL tDSS tDSH tMRD tWPST tWPRE tIH tIS tRPRE tRPST DDR2-533 min -500 -450 0.45 0.45 min(tCL, tCH) 3750 225 100 0.6 0.35 x tAC min 2* tACmin x x tHP - tQHS WL-0.25 0.35 0.35 0.2 0.2 2 0.4 0.35 375 250 0.9 0.4 7.5 10 37.5 50 2 15 tWR+tRP 7.5 7.5 tRFC + 10 200 2 2 6 - AL x x x x x max +500 +450 0.55 0.55 x 8000 x x x x tAC max tAC max tAC max 300 400 x WL+0.25 x x x x x 0.6 x x x 1.1 0.6 x x
DDR2 SDRAM
DDR2-400 min -600 -500 0.45 0.45 min(tCL, tCH) 5000 275 150 0.6 0.35 x tAC min 2* tACmin x x tHP - tQHS WL-0.25 0.35 0.35 0.2 0.2 2 0.4 0.35 475 350 0.9 0.4 7.5 10 37.5 50 2 15 tWR+tRP 10 7.5 tRFC + 10 200 2 2 6 - AL x x x x x max +600 +500 0.55 0.55 x 8000 x x x x tAC max tAC max tAC max 350 450 x WL+0.25 x x x x x 0.6 x x x 1.1 0.6 x x
Units ps ps tCK tCK ps ps ps ps tCK tCK ps ps ps ps ps ps tCK tCK tCK tCK tCK tCK tCK tCK ps ps tCK tCK ns ns ns ns tCK ns tCK ns ns ns tCK tCK tCK tCK
Notes
Active to active command period for 1KB page size products tRRD Active to active command period for 2KB page size products tRRD Four Activate Window for 1KB page size products Four Activate Window for 2KB page size products CAS to CAS command delay Write recovery time Auto precharge write recovery + precharge time Internal write to read command delay Internal read to precharge command delay Exit self refresh to a non-read command Exit self refresh to a read command Exit precharge power down to any non-read command Exit active power down to read command Exit active power down to read command (Slow exit, Lower power) tFAW tFAW tCCD tWR tDAL tWTR tRTP tXSNR tXSRD tXP tXARD tXARDS
Rev. 1.5 Aug. 2005
256MB, 512MB, 1GB Unbuffered SODIMMs
Parameter CKE minimum pulse width (high and low pulse width) ODT turn-on delay ODT turn-on ODT turn-on(Power-Down mode) ODT turn-off delay ODT turn-off ODT turn-off (Power-Down mode) ODT to power down entry latency ODT power down exit latency OCD drive mode output delay Symbol tCKE tAOND tAON tAONPD tAOFD tAOF tAOFPD tANPD tAXPD tOIT DDR2-533 min 3 2 tAC(min) tAC(min)+2 2.5 tAC(min) tAC(min)+2 3 8 0 tIS+tCK +tIH 12 2 tAC(max)+1 2tCK+tAC( max)+1 2.5 tAC(max)+ 0.6 max 3 2 tAC(min) tAC(min)+2 2.5 tAC(min) min
DDR2 SDRAM
DDR2-400 max 2 tAC(max)+1 2tCK+tAC (max)+1 2.5 tAC(max)+ 0.6 2.5tCK+ tAC(max)+1 Units tCK tCK ns ns tCK ns ns tCK tCK 12 ns ns Notes
2.5tCK+ tAC(min)+2 tAC(max)+1 3 8 0 tIS+tCK +tIH
Minimum time clocks remains ON after CKE asynchronously tDelay drops LOW
Rev. 1.5 Aug. 2005
256MB, 512MB, 1GB Unbuffered SODIMMs
Physical Dimensions: 32Mbx16 based 64Mx64 Module(2 Rank)
M470T6554BG(Z)3/M470T6554BG(Z)0
67.60 mm 2.00
DDR2 SDRAM
3.8 mm Max
4.00 0.10
6.00
1 11.40 16.25
a
b
199
20.00
30.00
47.40 63.00
1.1 mm Max
2
a SPD
200
67.60 mm
DETAIL a
30.00
DETAIL b
FRONT SIDE
4.20 2.70 0.10 1.50 0.10
BACK SIDE
4.00 0.10 1.0 0.05 0.20 0.15
2.55
1.80 0.10 4.00 0.10 1.0 0.05 4.20
2.40 0.10 0.60 0.45 0.03
The used device is 32M x16 DDR2 SDRAM, FBGA. DDR2 SDRAM Part NO : K4T51163QB
Rev. 1.5 Aug. 2005
256MB, 512MB, 1GB Unbuffered SODIMMs
Physical Dimensions: 32Mbx16 based 32Mx64 Module(1 Rank)
M470T3354BG(Z)3/M470T3354BG(Z)0
67.60 mm 2.00
DDR2 SDRAM
2.45 mm Max
30.00
4.00 0.10
6.00
SPD
1 11.40 16.25
a
b
199
47.40 63.00
20.00
1.1 mm Max
2
a
200
67.60 mm
DETAIL a
30.00
DETAIL b
FRONT SIDE
4.20 2.70 0.10 1.50 0.10
BACK SIDE
4.00 0.10 1.0 0.05 0.20 0.15
2.55
1.80 0.10 4.00 0.10 1.0 0.05 4.20
2.40 0.10 0.60 0.45 0.03
The used device is 32M x16 DDR2 SDRAM, FBGA. DDR2 SDRAM Part NO : K4T51163QB
Rev. 1.5 Aug. 2005
256MB, 512MB, 1GB Unbuffered SODIMMs
Physical Dimensions: 64Mbx8 based 128Mx64 Module(2 Ranks)
M470T2953BS(Y)3/M470T2953BS(Y)0
67.60 mm 2.00
SPD
DDR2 SDRAM
3.8 mm max
4.00 0.10
6.00
1 11.40 16.25
a
b 47.40 63.00
199
20.00
30.00
1.1mm max
2
a
200
67.60 mm
DETAIL a
30.00
DETAIL b
FRONT SIDE
4.20 2.70 0.10 1.50 0.10
BACK SIDE
4.00 0.10 1.0 0.05 0.20 0.15
2.55
1.80 0.10 4.00 0.10 1.0 0.05 4.20
2.40 0.10 0.60 0.45 0.03
The used device is 64M x8 DDR2 SDRAM, FBGA. DDR2 SDRAM Part NO : K4T51083QB
Rev. 1.5 Aug. 2005
256MB, 512MB, 1GB Unbuffered SODIMMs
Revision History
Revision 1.0 (Jan. 2004)
- Initial Release
DDR2 SDRAM
Revision 1.1 (Jun. 2004)
- Added lead-free part number in the ordering information - Changed IDD2P
Revision 1.2 (Jul. 2004)
- Added current values and part number of low power product
Revision 1.3 (Feb. 2005)
- Added the detail information for mechanical dimension
Revision 1.4 (Mar. 2005)
- Changed 1GB Functional Block Diagram
Revision 1.5 (Aug. 2005)
- Changed the IDD Specification Parameters Definition
Rev. 1.5 Aug. 2005

▲Up To Search▲

Price & Availability of M470T2953BS0-CD5CC

	To Download M470T2953BS0-CD5CC Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .